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Low Voltage Integrated DDR Termination Regulator
POWER MANAGEMENT Description
The SC2596 is an integrated linear DDR termination device, which provides a complete solution for DDR termination regulator designs; while meeting the JEDEC requirements of SSTL-2 and SSTL-18 specifications for DDR-SDRAM termination. The SC2596 regulates up to +/- 2.5A for DDR-I and +/1.5A for DDR-II application requirements. VTT is regulated to track the VREF voltage over the entire current range with shoot through protection. A V SENSE pin is incorporated to provide excellent load regulation, along with a buffered reference voltage for internal use. The SC2596 also features a disable function which is to tri-state the output during Suspend To Ram (STR) states by pulling the EN pin low.
SC2596
Features
Sourcing or sinking 2.5A for DDR-I Sourcing or sinking 1.5A for DDR-II AVCC undervoltage lockout Reference output Minimum number of external components Accurate internal voltage divider Disable function, puts device into sleep mode Thermal shutdown Over current protection Available in SOIC-8 EDP package WEEE and RoHS compliant
Applications
DDR-I and DDR-II memory termination SSTL-2 and SSTL-3 termination HSTL termination PC motherboards Graphics boards Disk drives CD-ROM drives
Typical Application Circuit
AVCC
EN VDDQ
SC2596 EN VDDQ PVCC
AVCC
VTT
VTT
VSENSE VREF VREF
GND
0
Revision: July 18, 2007
1
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SC2596
POWER MANAGEMENT Absolute Maximum Ratings
P a r a m et er PVCC, AVCC, VDDQ to GND Maximum Junction Temperature Range Storage Temperature Range Peak IR Reflow Temperature 10-40S ESD Rating (Human Body Model) Symb ol VCC TJ TSTG T PKG ESD M a xi m u m -0.3 to +6.0 -40 to +125 -65 to +150 260 2
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Un i ts V
O
C C C
O
O
kV
Electrical Characteristics (DDR-I)
Unless otherwise specified: TJ = -40oC to +125oC, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
P ar am et er Reference Voltage VREF Output Impedance V TT Output Regulation
(1)
S y m b ol V REF ZVREF (VTT - VREF)
Te s t C o n d i t i o n s IREF_OUT = 0mA IREF = -30uA to +30uA IOUT = 0A IOUT = -1.5A IOUT = +1.5A ILOAD = 0A
Min 0.49VDDQ
Ty p 0.5VDDQ 230
M ax 0.51VDDQ
Units V
-25
0 400 2.1
+25 700 2.2
mV uA V k
Quiescent Current AVCC Enable Threshold VDDQ Input Impedance Quiescent Current in Shutdown EN Pin Leakage Current EN Threshold Voltage V TT Leakage Current in Shutdown
IQ
ZVDDQ ISD IQ_SD VH VL IV TT_L SD = 0V, V TT = 1.25V, at 25 OC EN = 0 EN = 0 2
100 150 250 1 0.8 6
uA uA V uA
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SC2596
POWER MANAGEMENT Electrical Characteristics (DDR-I Cont.)
Unless otherwise specified: TJ = -40oC to +125oC, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
P ar am et er VSEN SE Current Thermal Shutdown Thermal Shutdown Hysteresis
S y m b ol
Te s t C o n d i t i o n s
Min
Ty p 50 160 10
M ax 200
Units nA
O
ISENSE
TSD TSD_HYS
C C
O
Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, TA = 25 oC)
Electrical Characteristics (DDR-II)
Unless otherwise specified: TJ = -40oC to +125oC, AVCC = 3.3V, PVCC = VDDQ = 1.8V.
P ar am et er Reference Voltage VREF Outp ut Impedance V TT Outp ut Regulation
(1)
S y m b ol V REF ZVREF (VTT - VREF)
Te s t C o n d i t i o n s IREF_OUT = 0mA IREF = -30uA to +30uA IOUT = 0A IOUT = -1.0A IOUT = +1.0A ILOAD = 0A
Min 0.49VDDQ
Ty p 0.5VDDQ 230
M ax 0.51VDDQ
Units V
-25
0 400 2.1
+25 700 2.2
mV uA V k
Quiescent Current AVCC Enable Threshold VDDQ Inp ut Impedance Quiescent Current in Shutdown EN Pin Leakage Current EN Threshold Voltage V TT Leakage Current in Shutdown VSEN SE Current Thermal Shutdown Thermal Shutdown Hysteresis
IQ
ZVDDQ ISD IQ_SD VH VL IV TT_L SD = 0V, V TT = 0.9V, at 25 OC EN = 0 EN = 0 2
100 150 0.5 0.8 6 50 160 10 200 250
uA uA V uA nA
O
ISENSE
TSD TSD_HYS
C C
O
Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, TA = 25 oC)
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SC2596
POWER MANAGEMENT Waveforms PRELIMINARY
AVCC
AVCC
VDDQ//PVCC Vref VTT
Start up.
VDDQ//PVCC
VREF
VTT
Shut down.
AVCC PVCC EN VTT
Start up by EN.
AVCC PVCC EN VTT
Shut down by EN.
AVCC PVCC VTT IO
AVCC PVCC//VDDQ VTT IO
1A load
(c) 2007 Semtech Corp. 4
Transient with +/- 1A load
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SC2596
POWER MANAGEMENT Waveforms
4.0 Output Current (A)
Output Current (A) 4.0 3.5 3.0 2.5 2.0
3.5 3.0 2.5 2.0 2 2.5 3 3.5 4 4.5 5 5.5
2
2.5
3
3.5
4
4.5
5
5.5
AVCC (V)
AVCC (V)
Maximum Sourcing Current vs AVCC. (VDDQ=1.8V, PVCC=2.5V)
Maximum Sinking Current vs AVCC. (VDDQ=1.8V, PVCC=2.5V)
3.0 Output Current (A)
Output Current (A)
4.0 3.5 3.0 2.5 2.0
2.5 2.0 1.5 1.0 2 2.5 3 3.5 4 4.5 5 5.5
2
2.5
3
3.5
4
4.5
5
5.5
AV (V) CC
Maximum Sourcing Current vs AVCC. (VDDQ=1.8V, PVCC=1.8V)
AVCC(V)
Maximum Sinking Current vs AVCC. (VDDQ=1.8V, PVCC=1.8V)
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SC2596
POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information
P ar t N u m b er P a c k a g e ( 3) SOIC-8L EDP Te m p . R a n g e ( T A ) -40 to +105 OC
TOP VIEW
GND EN VSENSE VREF 1 2 3 4 8 7 6 5 VTT PVCC AVCC VDDQ
SC2596SETRT(1) SC2596EVB (2)
Evaluation Board
Notes: (1)Only available in tape and reel packaging. A reel contains 2500 devices for EDP SOIC-8. (2) EVB provided with EDP SOIC-8 package. (3) Lead free product. This product is fully WEEE and RoHS compliant.
(SOIC-8L-EDP)
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SC2596
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 P i n N am e GN D EN VSEN SE Ground. Enable p in. SC2596 is disabled when EN p in is low. VSEN SE p in is a feedback p in. Connect a 10nF to 100nF Ceramic cap acitor between this p in to ground and p lace this cap acitor close to VSEN SE p in is required to avoid oscillation during transient condition. VREF p in is an outp ut p in, which p rovides the buffered outp ut of the internal reference voltage. A 100nF ceramic cap acitor should be connected from VREF p in to ground with shor t trace. The VDDQ p in is an inp ut p in for creating internal reference voltage to regulate V TT. The VDDQ voltage is connected to an internal resistor divider. The central tap of resistor divider (VDDQ/2) is connected to the internal voltage buffer, which outp ut is connected to VREF p in and the non-inver ting inp ut of the error amp lifier as the reference voltage. With the feedback loop closed, the V TT outp ut voltage will always track the VDDQ/2 p recisely. It is recommended that a 1uF ceramic cap acitor should be added next to the VDDQ p in to ground to increase the noise immunity. The AVCC p in is used to sup p ly all of the internal control circuitry. The AVCC voltage has to be greater than its UVLO threshold voltage (2.1V typ ical) to allow the SC2596 to be in normal op eration. If AVCC voltage is lower than the UVLO threshold voltage, the V TT p in should be in high imp edance status. The PVCC p in p rovides the rail voltage from where the V TT p in draws load current. There is a limitation between AVCC and PVCC. The PVCC voltage must be less or equal to AVCC voltage to ensure the correct outp ut voltage regulation. The V TT source current cap ability is dep endent on PVCC voltage. Higher the voltage on PVCC, higher the source current. The V TT p in is the outp ut of SC2596. It can sink and source continuous current while keep ing excellent load regulation. It is recommended that one should use at least one 220uF low ESR cap acitor and a 1uF ceramic cap acitor or on e 220u F h i gh ESR electrol y ti c cap aci tor an d a 6.8u F cerami c cap aci tor, which are p laced on the V TT strip p lane to ground reducing the voltage sp ike under load transient condition. Pad for heatsinking p urp oses. Connect to ground p lane using multip le vias. N ot connected internally. P i n Fu n c t i o n
4
V REF
5
VDDQ
6
AVCC
7
PVCC
8
V TT
THERMAL PAD
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SC2596
POWER MANAGEMENT Block Diagram
EN
PRELIMINARY
AVCC
PVCC
VDDQ
UVLO + Thermal Shutdown
+ + -
AntiShootthru + Driver Circuit
VTT
Vref Buffer
Error Am p.
GND
VREF
Vsense
Description SC2596 is a low-voltage, low-dropout DDR termination regulator with separate power supply to support both DDR1 and DDR2 applications. AVCC and PVCC can be tied together for DDR1 and can also be separated for DDR2. SC2596 regulates VTT to the voltage of VREF. VTT will sink or source upto 2.5A. Internal shoot-through protection ensure both top and bottom MOSFET will not conduct while maintaining fast source-to-sink load transient. Thermal shut-down and internal current limit protect SC2596 from shorted load or over-heated VREF BUFF VREF is derived from VDDQ with an accurate divide by op-amps(VREF Buffer). It is capable to sink and source 30uA. It is used as the reference voltage to the Error amp. A 100nF or higher capacitor is recommended for VREF pin to ground; To enhance the noise immunity from board, an additional pull-down resistor (1M) is recomanded as well from VREF pin to ground.
ERROR AMP Low input offset op-amp for the main linear regulator. It controls the VTT output voltage and which side of the MOSFET to turn on (or turn off) to achieve zero shoot through current. ANTI-Shoot Thought Driver Buffer stage takes the error voltage to control MOSFET. Internal current limit is incorporated to protect from shorted load.
THERMAL SHUTDOWN & UVLO The Thermal shutdown block prevent the junction temperature exceed 165 oC. UVLO circuit to ensure proper power is available for correct operation of the IC.
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SC2596
POWER MANAGEMENT Application Information
Overview Double Data Rate (DDR) SDRAM was defined by JEDEC 1997. Its clock speed is the same as previous SDRAM but data transfer speed is twice than previous SDRAM. By now, the requirement voltage range is changed from 3.3V to 2.5V or 1.8V; the power dissipation is smaller than SDRAM. For above reasons, it is very popular and widely used in M/B, N/B, Video-cards, CD ROM drives, Disk drives. Regarding the DDR power management solution, there are two topologies can be selected for system designers. One is switching mode regulator that has bigger sink/ source current capability, but the cost is higher and needs more board space. Another solution is linear mode regulator, which costs less, and needs less board space. For two DIMM motherboards, system designers usually choose the linear mode regulator for DDR power management solution. Thermal shutdown The SC2596 has built-in thermal detected circuit to prevent this device from over temperature and damage. The SC2596 goes into shunt down mode when temperature is higher than 165OC. The protection condition will release when the temperature of device drop down by 10OC. AVCC and PVCC AVCC and PVCC are the input supply pins for the SC2596. AVCC is supply voltage for all the internal control circuitry. The AVCC voltage has to be greater than its UVLO threshold voltage (2.1V typical) to allow the SC2596 to be normal operation. The PVCC pin provides the rail voltage from where the VTT pin draws load current. There is a limitation between AVCC and PVCC. The PVCC voltage must be less or equal to AVCC voltage to ensure the correct VTT output voltage regulation. VSENSE VSENSE pin is a feedback pin from VTT plane. VTT plane is always a narrow and long strip plane in most montherboard applications. This long strip plane will
(c) 2007 Semtech Corp. 9
0
cause a large trace inductance and trace resistance. Consider the load transient condition, a fast load current going through VTT strip plane will create a voltage spike on VTT plane and a DC voltage drop for load current. It is recommanded the VSENSE pin should be connected center of VTT plane to improve regulation and transient response. A longer trace of VSENSE may pick up noise and cause the error of load regulation. Hence designer should avoid a longer trace between VSENSE to VTT plane. A 100nF ceramic capacitor close to VSENSE pin is required. VREF VREF pin is an output pin to provid internal reference voltage. System designer can use the voltage for Northbridge chipset and memory. It is necessary to add a ceramic capacitor (100nF) from VREF pin to ground with shortest trace. Typical Application Circuits & Waveforms Four different application circuits are shown below in Figure 1, Figure 2, Figure 3 and Figure 4. Each circuit is designed for a specific condition. See Note a. and b. below for recommended power up sequencing. Application_1: Standard SSTL-2 Application The AVCC pin, PVCC pin and the VDDQ pin can be tied together for SSTL-2 application (Figure 1). It only needs a 2.5V power rail for normal operation. System designer can save the PCB space and reduce the cost.
VDDQ
2.5V
SC2596 1 2 EN 3 VREF 4 VSENSE VREF AVCC VDDQ 6 5 Cin1 Cref 100nF 1uF 100uF 220uF Cin2 Cout GND EN VTT PVCC 8 7 VTT
1.25V
1.25V
10nF
Figure 1: Standard SSTL-2 application.
C sense
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SC2596
POWER MANAGEMENT Application Information (Cont.)
Application_2: Lower Power Loss Configuration for SSTL-2 If power loss is a major concern, separating the PVCC form AVCC and VDDQ will be a good choice (Figure 2). The PVCC can operate at lower voltage (1.8V to 2.5V) if 2.5V voltage is applied on AVCC and the VDDQ, the source current is lower due to the lower operating voltage applied on the PVCC.
SC2596 1 EN 2 3 VREF 4 GND EN VSENSE VREF VTT PVCC AVCC VDDQ 8 PVCC 7 6 5 Cin2 1uF Cin1 Cout VTT
PRELIMINARY
Application_3: High Source Current Configuration If there is a need for VTT to source more current, especially for DDR-II applications, the system designer can tie the AVCC and PVCC to 3.3V while has the VDDQ tie to 1. 8V. This configuration can ensure more than 2A source and sink capability from the VTT rail.
SC2596 1 2 GND EN VSENSE VREF VTT PVCC AVCC VDDQ 8 3.3V 7 6 VDDQ 5 VTT
0.9V
2.5V
VDDQ
1.25V
EN 3 VREF 4
2.5V
1.8V
Cin1 Cin2 Cout
2.5V
Csense
0.9V
Csense
1M Cref 100nF
1.25V
10nF Cref 100nF
1uF
100uF 220uF
10nF
100uF 220uF
0
Figure 4: High current set up for SSTL-18(DDR-II).
0
Figure 2: Lower power loss for SSTL-2(DDR-I).
SC2596 1 2 EN 3 VREF 4 VSENSE VREF AVCC VDDQ 6 VDDQ 5 GND EN VTT PVCC 8 2.5V 7 VTT
Notes: (a) The preferred configuration for DDR-I applications is to tie AVCC and PVCC to VDDQ, which is typically 2.5V. (b) If AVCC and PVCC rails are tied together, then the VDDQ cannot lead the AVCC and PVCC.
0.9V
1.8V
Cin1 Cin2 Cout
0.9V
Csense
Cref 100nF 1uF 100uF 220uF
10nF
0
Figure 3: Lower power loss for SSTL-18(DDR-II).
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SC2596
POWER MANAGEMENT Application Information (Cont.)
Layout guidelines 1) The EDP SO-8 package of SC2596 can improve the thermal impedance (JC) significantly. A suitable thermal pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern. 2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the VREF pin with the shortest connection trace. 3) To reduce the noise on input power rail for standard SSTL-2 application, a 100F low ESR capacitor and a 1F ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection. 4) VTT output copper plane should be as large as possible. A 4.7uF to 10F capacitor have to be used to decouple the VTT pin. 5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor close this vsense pin.
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SC2596
POWER MANAGEMENT Typical Application Circuit PRELIMINARY
VDDQ
1.8V
U3 1 EN 2 3 4 VREF GND EN VSENSE VREF SC2596 VTT PVCC AVCC VDDQ 8 7 6 5 VTT
0.9V
3.3V
0.9V
R1 1M
C1 C2 100nF 10nF
C3 1uF
C4 100uF
C5 220uF
0
DDR-II VTT Solution
Bill of Material
R ef 1 2 3 4 5 6 7 8 Qty 1 1 1 1 1 1 1 1 R ef eren ce C1 C2 C3 C6 C4 C5 R1 U1 P ar t N u m b e r / Val u e 100nF, 25V, X5R,Ceramic, 0603 10nF, 16V, X5R, Ceramic , 0603 1uF, 16V, X5R, Ceramic , 0603 10uF, 16V, X5R, Ceramic , 1206 100uF, 6.3V, Aluminum 220uF, 6.3V, Aluminum 1M OHM SC2596 Yageo Yageo Yageo Yageo Yageo Rubycon Yageo Semtech M an u f act u r er
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SC2596
POWER MANAGEMENT
Outline Drawing - Power SOIC-8L (EDP)
A N 2X E/2 E1 E e D
DIM
A A1 A2 b c D E1 E e F h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.053 .069 .000 .005 .049 .065 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .086 .090 .094 .010 .020 .016 .028 .041 (.041) 8 0 8 .004 .010 .008 1.75 1.35 0.13 0.00 1.65 1.25 0.31 0.51 0.25 0.17 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 2.19 2.29 2.39 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0 8 0.10 0.25 0.20
1 ccc C 2X N/2 TIPS
2 e/2 B D
aaa C SEATING PLANE A2 A C bxN bbb F EXPOSED PAD A1 C A-B D
h
H F GAGE PLANE 0.25
h
c
L (L1)
01
SEE DETAIL SIDE VIEW
NOTES: 1. 2. 3. 4.
A
DETAIL
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS-012, VARIATION BA.
Land Pattern - Power SOIC-8L (EDP)
E D SOLDER MASK
DIM
(C) F G Z C D E F G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.205) .098 .201 .096 .118 .050 .024 .087 .291 (5.20) 2.49 5.10 2.44 3.00 1.27 0.60 2.20 7.40
Y THERMAL VIA ? 0.36mm P X
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 300A. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
2. 3.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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